1. Field of the Invention
The present invention relates to an apparatus for inputting a clock signal and data signals of a small amplitude level such as a data line driver of a liquid crystal display (LCD) apparatus.
2. Description of the Related Art
Generally, an LCD apparatus is constructed by an LCD panel having data lines (or signal lines), scan lines (or gate lines) and liquid crystal cells each located at one intersection between the data lines and the scan lines, a plurality of data line drivers provided at a horizontal edge of the LCD panel and connected by a cascade connection to each other for driving the data lines, and a plurality of scan line drivers provided at a vertical edge of the LCD panel and connected by a cascade connection to each other to drive the scan lines.
In an extended graphics array (XGA) formed by 1024×3×768 dots, eight data line drivers each for driving 384 (=128×3) data lines are provided. In this case, use is made of a low speed CMOS interface or a low speed large amplitude interface between modules of the drivers and their controller using a clock frequency of about 60 MHz.
On the other hand, in a super extended graphics array (SXGA) formed by 1280×3×1024 dots, ten data line drivers each for driving 384 (=128×3) data lines are provided. Also, in an ultra extended graphics array (UXGA) formed by 1600×3×1200 dots, sixteen data line drivers each for driving 300 (=100×3) data lines are provided. In both of these cases, although use is made of a high speed CMOS interface, such a high speed CMOS interface needs to adopt a parallel transmission system in order to avoid electro magnetic interference (EMI) noise, which, however, increases the number of connections. Therefore, use is now made of a high speed small amplitude interface between modules of the drivers and their controller using a clock frequency of higher than 60 MHz.
In the SXGA or UXGA using the above-mentioned high speed small amplitude interface, a receiver formed by a clock signal receiver (differential amplifier) and data signal receivers (differential amplifiers) are required. Also, in order to decrease the power consumption, the clock signal receiver and the data signal receivers are both activated only from a timing of generation of a start signal to a timing of completion of latching all data signals (see; JP-11-249626).
In the above-described prior art, however, since the restoration of the data signal receivers from a deactivation state to an activation state requires a certain time, the clock signal receiver needs to be activated sufficiently before the activation of the data signal receivers. For simply realizing this, the clock receiver was always activated. This increases the power consumption.